Figure 1.2 Internal Block Diagram Of H8S/2366 - Renesas H8S/2368 Series Hardware Manual

MD2
MD1
MD0
EXTAL
XTAL
EMLE
NMI
φ
PF7/
PF6/
PF5/
PF4/
PF3/
PF2/
PF1/
PF0/
PG6/
PG5/
PG4/ /
PG3/
PG2/
PG1/
PG0/
P85/SCK3
P83/RxD3
P81/TxD3
Rev. 2.00, 05/03, page 4 of 820
PLL
Clock
pulse
generator
Interrupt controller
ROM
(Flash memory)
RAM
TPU × 6 channels
TMR × 2 channels
Port 1 Port 2

Figure 1.2 Internal Block Diagram of H8S/2366

Port D Port E
H8S/2000 CPU
DTC
WDT
SCI × 5 channels
2
I C bus interface 2 (option)
8-bit D/A converter
10-bit A/D converter
Port 4
PA7/A23/ /
PA6/A22/
PA5/A21/
PA4/A20/
PA3/A19
PA2/A18
PA1/A17
PA0/A16
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PB1/A9
PB0/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
P35/SCK1/SCL0
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
P53/ //
P52/SCK2/
P51/RxD2/
P50/TxD2/
Port 9