Renesas H8S/2368 Series Hardware Manual page 266

Bit Bit Name
3 DTIE1B
2 DTIE1A
1 DTIE0B
0 DTIE0A
Rev. 2.00, 05/03, page 214 of 820
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Data Transfer End Interrupt Enable 1B
Data Transfer End Interrupt Enable 1A
Data Transfer End Interrupt Enable 0B
Data Transfer End Interrupt Enable 0A
These bits enable or disable an interrupt to the
CPU or DTC when transfer ends. If the DTIE bit
is set to 1 when DTE = 0, the DMAC regards
this as indicating the end of a transfer, and
issues a transfer end interrupt request to the
CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE bit to 1.