Renesas H8S/2368 Series Hardware Manual page 46

Figure 24.15 DRAM Access Timing: Two-State Burst Access.................................................. 754
Figure 24.16 DRAM Access Timing: Three-State Access (RAST = 1) ..................................... 755
Figure 24.17 DRAM Access Timing: Three-State Burst Access ................................................ 756
Figure 24.18 CAS-Before-RAS Refresh Timing ........................................................................ 757
Figure 24.19 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion)............................ 757
Figure 24.20 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) ............. 757
Figure 24.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) ............. 758
Figure 24.22 External Bus Release Timing................................................................................. 758
Figure 24.23 External Bus Request Output Timing .................................................................... 759
Figure 24.24 DMAC Single Address Transfer Timing: Two-State Access ................................ 760
Figure 24.25 DMAC Single Address Transfer Timing: Three-State Access .............................. 761
Figure 24.26 DMAC TEND Output Timing ............................................................................... 761
Figure 24.27 DMAC DREQ Input Timing ................................................................................. 762
Figure 24.28 I/O Port Input/Output Timing ................................................................................ 764
Figure 24.29 PPG Output Timing ............................................................................................... 764
Figure 24.30 TPU Input/Output Timing...................................................................................... 764
Figure 24.31 TPU Clock Input Timing ....................................................................................... 765
Figure 24.32 8-Bit Timer Output Timing.................................................................................... 765
Figure 24.33 8-Bit Timer Clock Input Timing............................................................................ 765
Figure 24.34 8-Bit Timer Reset Input Timing............................................................................. 765
Figure 24.35 WDT Output Timing ............................................................................................. 766
Figure 24.36 SCK Clock Input Timing ....................................................................................... 766
Figure 24.37 SCI Input/Output Timing: Synchronous Mode...................................................... 766
Figure 24.38 A/D Converter External Trigger Input Timing ...................................................... 766
2
Figure 24.39 I C Bus Interface Input/Output Timing (Option)................................................... 767
Appendix
Figure C.1 Package Dimensions (TFP-120) ............................................................................ 793
Figure C.2 Package Dimensions (FP-128B) ............................................................................ 794
Timing of Address Bus, RD, HWR, and LWR
Figure D.1
(8-bit bus, 3-state access, no wait) ......................................................................... 796
Rev. 2.00, 05/03, page xlvi of lii