Figure 14.1 Block Diagram Of Sci - Renesas H8S/2368 Series Hardware Manual

115.152 or 460.606 kbps at 10.667 MHz operation
115.196, 460.784 or 720 kbps at 16 MHz operation
720 kbps at 32 MHz operation
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Smart Card Interface
• Automatic transmission of error signal (parity error) in receive mode
• Error signal detection and automatic data retransmission in transmit mode
• Direct convention and inverse convention both supported
RDR
RxD
RSR
TxD
SCK
Legend
RSR : Receive shift register
RDR : Receive data register
TSR : Transmit shift register
TDR : Transmit data register
SMR : Serial mode register
SCR : Serial control register
SSR : Serial status register
SCMR : Smart card mode register
BRR : Bit rate register
SEMR : Serial extension mode register (only in SCI_2)
Rev. 2.00, 05/03, page 508 of 820
Module data bus
SCMR
TDR
SSR
SCR
SMR
TSR
SEMR
Transmission/
reception control
Parity generation
Parity check

Figure 14.1 Block Diagram of SCI

BRR
Baud rate
generator
Clock
External clock
TEI
TXI
RXI
ERI
Internal
data bus
φ
φ/4
φ/16
φ/64
Average transfer
rate generator
(SCI_2)
10.667 MHz operation
• 115.152 kbps
• 460.606 kbps
16 MHz operation
• 115.196 kbps
• 460.784 kbps
• 720 kbps
32 MHz operation
• 720 kbps