Figure 24.15 Dram Access Timing: Two-State Burst Access - Renesas H8S/2368 Series Hardware Manual

A23 to A0
,
,
Read
D15 to D0
,
Write
D15 to D0
,
Notes:
timing: when DDS = 1
timing: when RAST = 1

Figure 24.15 DRAM Access Timing: Two-State Burst Access

Rev. 2.00, 05/03, page 754 of 820
T T
p r
T T
c1 c2
t
RCH
t
RCS1
t t
DACD1
T T
c1 c2
t
CPW1
t
AC3
DACD2