Figure 7.39 Dmac Register Update Timing; Figure 7.40 Contention Between Dmac Register Update And Cpu Read - Renesas H8S/2368 Series Hardware Manual

DMA Internal
address
Idle
DMA control
DMA register
[1]
operation
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2']Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
Note: In single address transfer mode, the update timing is the same as [1].
The MAR operation is post-incrementing/decrementing of the DMA internal address value.
• If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
register is read as shown in figure 7.40.
DMA internal
address
DMA control
DMA register
operation
Note: The lower word of MAR is the updated value after the operation in [1].

Figure 7.40 Contention between DMAC Register Update and CPU Read

Rev. 2.00, 05/03, page 270 of 820
DMA transfer cycle
DMA read DMA write
Transfer
Transfer
destination
source
Read
Write
[2]

Figure 7.39 DMAC Register Update Timing

CPU longword read
MAR upper
word read
Idle
Transfer
source
Read
Idle
[1]
DMA transfer cycle
MAR lower
word read DMA read
Transfe Transfer
destination
source
Write
Read
[1] [2]
DMA last transfer cycle
DMA read
DMA write
Transfer
destination
Write Dead
[2'] [3]
DMA write
Idle
DMA
dead
Idle