Renesas H8S/2368 Series Hardware Manual page 45

Figure 19.1 Block Diagram of Flash Memory .........................................................................646
Figure 19.2 Flash Memory State Transitions ............................................................................647
Figure 19.3 Boot Mode .............................................................................................................648
Figure 19.4 User Program Mode...............................................................................................649
Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7) .....................651
Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode.......................661
Figure 19.7 Flowchart for Flash Memory Emulation in RAM..................................................662
Figure 19.8 Example of RAM Overlap Operation ....................................................................663
Figure 19.9 Program/Program-Verify Flowchart ......................................................................665
Figure 19.10 Erase/Erase-Verify Flowchart................................................................................667
Figure 19.11 Power-On/Off Timing............................................................................................671
Figure 19.12 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode) ............................672
Section 20 Mask ROM
Figure 20.1 Block Diagram of 256-kbyte Mask ROM (HD6432365) ......................................673
Section 21 Clock Pulse Generator
Figure 21.1 Block Diagram of Clock Pulse Generator..............................................................675
Figure 21.2 Connection of Crystal Oscillator (Example)..........................................................678
Figure 21.3 Crystal Oscillator Equivalent Circuit .....................................................................678
Figure 21.4 External Clock Input (Examples)...........................................................................679
Figure 21.5 External Clock Input Timing .................................................................................680
Figure 21.6 Note on Oscillator Board Design ...........................................................................682
Figure 21.7 Recommended External Circuitry for PLL Circuit ................................................682
Section 22 Power-Down Modes
Figure 22.1 Mode Transitions ...................................................................................................685
Figure 22.2 Software Standby Mode Application Example......................................................693
Figure 22.3 Hardware Standby Mode Timing...........................................................................694
Section 24 Electrical Characteristics
Figure 24.1 Output Load Circuit ...............................................................................................737
Figure 24.2 System Clock Timing ............................................................................................738
Figure 24.3 Oscillation Stabilization Timing (1) ......................................................................739
Figure 24.3 Oscillation Stabilization Timing (2) ......................................................................739
Figure 24.4 Reset Input Timing ................................................................................................740
Figure 24.5 Interrupt Input Timing ...........................................................................................741
Figure 24.6 Basic Bus Timing: Two-State Access....................................................................745
Figure 24.7 Basic Bus Timing: Three-State Access..................................................................746
Figure 24.8 Basic Bus Timing: Three-State Access, One Wait ................................................747
Figure 24.9 Basic Bus Timing: Two-State Access (CS Assertion Period Extended)................748
Figure 24.10 Basic Bus Timing: Three-State Access (CS Assertion Period Extended)..............749
Figure 24.11 Burst ROM Access Timing: One-State Burst Access ............................................750
Figure 24.12 Burst ROM Access Timing: Two-State Burst Access ...........................................751
Figure 24.13 DRAM Access Timing: Two-State Access............................................................752
Figure 24.14 DRAM Access Timing: Two-State Access, One Wait ..........................................753
Rev. 2.00, 05/03, page xlv of lii