Renesas H8S/2368 Series Hardware Manual page 39

Figure 6.33 RTCNT Operation .................................................................................................169
Figure 6.34 Compare Match Timing .........................................................................................169
Figure 6.35 CBR Refresh Timing .............................................................................................170
Figure 6.36 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) ...............170
Figure 6.37 Example of CBR Refresh Timing (CBRM = 1).....................................................171
Figure 6.38 Self-Refresh Timing...............................................................................................172
Figure 6.39 Example of Timing when Precharge Time after Self-Refreshing is Extended
by 2 States..............................................................................................................173
Example of DACK Output Timing when DDS = 1 (RAST = 0, CAST = 0).........174
Figure 6.40
Example of DACK Output Timing when DDS = 0 (RAST = 0, CAST = 1).........175
Figure 6.41
Figure 6.42 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) ............177
Figure 6.43 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) ............178
Figure 6.44 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)...........179
Figure 6.45 Example of Idle Cycle Operation (Write after Read).............................................180
Figure 6.46 Example of Idle Cycle Operation (Read after Write) ............................................181
Figure 6.47 Relationship between Chip Select (CS) and Read (RD) ........................................182
Figure 6.48 Example of DRAM Full Access after External Read (CAST = 0) ........................182
Figure 6.49 Example of Idle Cycle Operation in RAS Down Mode
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0).........183
Figure 6.50 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)
(IDLC = 0, RAST = 0, CAST = 0) ........................................................................183
Figure 6.51 Example of Idle Cycle Operation after DRAM Access
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0).........184
Figure 6.52 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0) ..........................................185
Figure 6.53 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0).......................................................186
Figure 6.54 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
and Write Accesses to DRAM Space in RAS Down Mode...................................188
Figure 6.55 Example of Timing when Write Data Buffer Function is Used.............................190
Figure 6.56 Bus Released State Transition Timing...................................................................193
Section 7 DMA Controller (DMAC)
Figure 7.1 Block Diagram of DMAC......................................................................................200
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)............................................224
Figure 7.3 Operation in Sequential Mode ...............................................................................231
Figure 7.4 Example of Sequential Mode Setting Procedure....................................................232
Figure 7.5 Operation in Idle Mode..........................................................................................233
Figure 7.6 Example of Idle Mode Setting Procedure ..............................................................234
Figure 7.7 Operation in Repeat mode......................................................................................236
Figure 7.8 Example of Repeat Mode Setting Procedure .........................................................237
Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified) ...........239
Figure 7.10 Example of Single Address Mode Setting Procedure
(When Sequential Mode is Specified)....................................................................240
Rev. 2.00, 05/03, page xxxix of lii