Figure 6.19 Example Of Timing When Chip Select Assertion Period Is Extended - Renesas H8S/2368 Series Hardware Manual

Address bus
Read
(when
RDNn = 0)
Data bus
,
Write
Data bus

Figure 6.19 Example of Timing when Chip Select Assertion Period is Extended

Both extension state T
basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non-
insertion can be specified for the T
register, and for the T
T
h
inserted before the basic bus cycle and extension state T
h
state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR
h
state with the lower 8 bits (CSXT7 to CSXT0).
t
Bus cycle
T T
1 2
Write data
Rev. 2.00, 05/03, page 151 of 820
T T
3 t
Read data
inserted after the
t