Figure 6.42 Example Of Burst Rom Access Timing (Astn = 1, 2-State Burst Cycle) - Renesas H8S/2368 Series Hardware Manual

Upper address bus
Lower address bus
Data bus
Note: n = 1, 0
Figure 6.42 Example of Burst ROM Access Timing
Full access
T T T
1 2 3
(ASTn = 1, 2-State Burst Cycle)
Burst access
T T T
1 2 1
Rev. 2.00, 05/03, page 177 of 820
T
2