Burst Operation; Figure 6.28 Example Of 2-Cas Dram Connection - Renesas H8S/2368 Series Hardware Manual

(Address shift size
set to 10 bits)
6.6.11

Burst Operation

With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making
consecutive accesses to the same row address. This mode enables fast (burst) access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
Burst Access (Fast Page Mode): Figures 6.29 and 6.30 show the operation timing for burst
access. When there are consecutive access cycles for DRAM space, the CAS signal and column
address output cycles (two states) continue as long as the row address is the same for consecutive
access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in
DRAMCR.
Rev. 2.00, 05/03, page 164 of 820
This LSI
n ( n)
( )
( )
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
D15 to D0

Figure 6.28 Example of 2-CAS DRAM Connection

2-CAS type 16-Mbit DRAM
1-Mbyte × 16-bit configuration
10-bit column address
A9
Row address input:
A8
A9 to A0
A7
Column address input:
A6
A9 to A0
A5
A4
A3
A2
A1
A0
D15 to D0