Figure 24.13 Dram Access Timing: Two-State Access - Renesas H8S/2368 Series Hardware Manual

A23 to A0
,
,
Read
D15 to D0
,
Write
D15 to D0
,
Notes:

Figure 24.13 DRAM Access Timing: Two-State Access

Rev. 2.00, 05/03, page 752 of 820
T
p
t
AD
t
AS3
t
PCH2
timing: when DDS = 0
timing: when RAST = 0
T T
r c1
t
AD
t
AH1
t
CSD2
t
AS2
t
OED1
t
AA3
t
AC4
t
WCS1
t
WRD2
t
WDS1
t
WDD
t
DACD1
T
c2
t
CSD3
t
AH2
t
CASD1
t
CASD1
t
CASW1
t
t
OED1
AC1
t t
RDS2 RDH2
t
WCH1
t
WRD2
t
WDH2
t
DACD2