Renesas H8S/2368 Series Hardware Manual page 574

Bit Bit Name
3 PER
2 TEND
1 MPB
0 MPBT
Notes: *1 Only 0 can be written, to clear the flag.
*2 Not supported by the H8S/2366.
Rev. 2.00, 05/03, page 522 of 820
Initial Value R/W
0 R/(W) *
1 R
0 R
0 R/W
Description
1
Parity Error
Indicates that a parity error occurred while
receiving in asynchronous mode and the reception
has ended abnormally.
[Setting condition]
When a parity error is detected during reception
If a parity error occurs, the receive data is
transferred to RDR but the RDRF flag is not set.
Also, subsequent serial reception cannot be
continued while the PER flag is set to 1. In
clocked synchronous mode, serial transmission
cannot be continued, either.
[Clearing condition]
When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains its
previous state when the RE bit in SCR is cleared
to 0.
Transmit End
[Setting conditions]
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit
of a 1-byte serial transmit character
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE
= 1
•
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
previous state is retained.
Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit to be added to
the transmit data.