Input/Output Pins; Register Descriptions; Table 7.1 Pin Configuration - Renesas H8S/2368 Series Hardware Manual

7.2

Input/Output Pins

Table 7.1 summarizes the pins of the interrupt controller.
Table 7.1 Pin Configuration
Channel Pin Name
0 DMA request 0
DMA transfer acknowledge 0 DACK0
DMA transfer end 0
1 DMA request 1
DMA transfer acknowledge 1 DACK1
DMA transfer end 1
7.3

Register Descriptions

• Memory address register_0AH (MAR_0AH)
• Memory address register_0AL (MAR_0AL)
• I/O address register_0A (IOAR_0A)
• Transfer count register_0A (ECTR_0A)
• Memory address register_0BH (MAR_0BH)
• Memory address register_0BL (MAR_0BL)
• I/O address register_0B (IOAR_0B)
• Transfer count register_0B (ECTR_0B)
• Memory address register_1AH (MAR_1AH)
• Memory address register_1AL (MAR_1AL)
• I/O address register_1A (IOAR_1A)
• Transfer count register_1A (ETCR_1B)
• Memory address register_1BH (MAR_1BH)
• Memory address register_1BL (MAR_1BL)
• I/O address register_1B (IOAR_1B)
• Transfer count register_1B (ETCR_1B)
• DMA control register_0A (DMACR_0A)
• DMA control register_0B (DMACR_0B)
• DMA control register_1A (DMACR_1A)
• DMA control register_1B (DMACR_1B)
Symbol I/O
DREQ0
Input
Output
TEND0
Output
DREQ1
Input
Output
TEND1
Output
Function
Channel 0 external request
Channel 0 single address
transfer acknowledge
Channel 0 transfer end
Channel 1 external request
Channel 1 single address
transfer acknowledge
Channel 1 transfer end
Rev. 2.00, 05/03, page 201 of 820