Section 1 Overview; Features - Renesas H8S/2368 Series Hardware Manual

1.1

Features

• High-speed H8S/2000 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
65 basic instructions
• Various peripheral functions
DMA controller (DMAC)*
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
Programmable pulse generator (PPG)*
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
2
I C bus interface 2 (IIC2)
10-bit A/D converter
8-bit D/A converter
Clock pulse generator
Note: * Not supported by the H8S/2366.
• On-chip memory
ROM Type
Flash memory version
Masked ROM version
ROMless version
• General I/O ports
I/O pins: 84
Input-only pins: 10
• Supports various power-down states
• Compact package

Section 1 Overview

Model ROM
HD64F2367 384 kbytes
HD64F2366 384 kbytes
HD6432365 256 kbytes

HD6412363
RAM Remarks
24 kbytes
30 kbytes In planning stage
16 kbytes
16 kbytes
Rev. 2.00, 05/03, page 1 of 820