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6.6.9
Wait Control
There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and
pin wait insertion using the WAIT pin.
Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and
to extend the write data setup time relative to the falling edge of CAS in a write access.
Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM
space is set to 1, from 0 to 7 wait states can be inserted automatically between the T
state and T
c1
c2
state, according to the WTCR setting.
Pin Wait Insertion: When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1, wait
input by means of the WAIT pin is enabled. When DRAM space is accessed in this state, a
) is first inserted. If the WAIT pin is low at the falling edge of φ in the last T
program wait (T
or
w
c1
state is inserted. If the WAIT pin is held low, T
T
state, another T
states are inserted until it
w
w
w
goes high.
Figures 6.25 and 6.26 show examples of wait cycle insertion timing in the case of 2-state and 3-
state column address output cycles.
Rev. 2.00, 05/03, page 160 of 820
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