Figure 15.14 Sample Flowchart For Master Transmit Mode - Renesas H8S/2368 Series Hardware Manual

16-bit single-chip microcomputer
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Start
Initialize
Read BBSY in ICCRB
No
BBSY=0 ?
Set MST = 1 and TRS
= 1 in ICCRA.
Write BBSY = 1
and SCP = 0.
Write transmit data
in ICDRT
Read TEND in ICSR
No
TEND=1 ?
Read ACKBR in ICIER
ACKBR=0 ?
Transmit
mode?
Write transmit data in ICDRT
Read TDRE in ICSR
No
TDRE=1 ?
No
Final byte?
Write transmit data in ICDRT
Read TEND in ICSR
No
TEND=1 ?
Clear TEND in ICSR
Clear STOP in ICSR
Write BBSY = 0
and SCP = 0
Read STOP in ICSR
No
STOP=1 ?
Set MST = 1 and TRS
= 0 in ICCRA
Clear TDRE in ICSR
End

Figure 15.14 Sample Flowchart for Master Transmit Mode

Rev. 2.00, 05/03, page 612 of 820
[1]
Test the status of the SCL and SDA lines.
[1]
[2]
Select master transmit mode.
Yes
[3]
Start condition issuance.
[2]
[4]
Select transmit data for the first byte (slave address + R/W),
[3]
and clear TDRE to 0.
[5]
Wait for 1 byte to be transmitted.
[4]
[6]
Test the acknowledge bit, transferred from the specified slave device.
[7]
Set transmit data for the second and subsequent data (except for the final byte),
[5]
and clear TDRE and TEND to 0.
[8]
Wait for ICDRT empty.
Yes
[9]
Set the final byte of transmit data, and clear TDRE and TEND to 0.
[6]
No
[10] Wait for the completion of transmission for the final byte.
Yes
[11] Clear TEND flag.
No
Master receive mode
Yes
[12] Clear STOP flag.
[7]
[13] Stop condition issuance.
[14] Wait for the creation of the stop condition.
[8]
[15] Set slave receive mode. Clear TDRE.
Yes
[9]
Yes
[10]
Yes
[11]
[12]
[13]
[14]
Yes
[15]

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