Figure 6.15 Bus Timing For 16-Bit, 3-State Access Space (Odd Address Byte Access) - Renesas H8S/2368 Series Hardware Manual

Bus cycle
T T T
1 2 3
Address bus
D15 to D8 Invalid
Read
D7 to D0 Valid
High
Write
High impedance
D15 to D8
D7 to D0 Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space
(Odd Address Byte Access)
Rev. 2.00, 05/03, page 146 of 820