Figure 10.15 Example Of Buffer Operation (1) - Renesas H8S/2368 Series Hardware Manual

TCNT value
TGRB_0
TGRA_0
H'0000
H'0200
TGRC_0
Transfer
TGRA_0
TIOCA
2. When TGR is an input capture register
Figure 10.16 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
H'0200
H'0450
H'0200

Figure 10.15 Example of Buffer Operation (1)

H'0450
H'0520
H'0450
Rev. 2.00, 05/03, page 421 of 820
H'0520
Time