Renesas H8S/2368 Series Hardware Manual page 419

•
PF2/CS6/LCAS*
The pin function is switched as shown below according to the combination of the operating mode,
bit EXPE, bits RMTS2 to RMTS0* in DRAMCR, bits ABW5 to ABW2 in ABWCR, and bit
PF2DDR.
Operating
mode
EXPE
Areas 2 to 5 Any
DRAM*
space
area is
16-bit bus
space
CS6E —
PF2DDR —
LCAS*
Pin function
output
Note: * Not supported by the H8S/2366.
•
PF1/CS5/UCAS*
The pin function is switched as shown below according to the combination of the operating mode,
bit EXPE, bits RMTS2 to RMTS0* in DRAMCR, and bit PF1DDR.
Operating
mode
EXPE
Areas Any of
2 to 5 areas
2 to 5 is
DRAM*/
synchro-
nous
DRAM
space
PF1DDR —
UCAS*
Pin function
output
Note: * Not supported by the H8S/2366.
1, 2, 4
—
All DRAM* space areas are 8-bit
bus space, or areas 2 to 5 are all
normal space
1 0
0 1 0
CS6
PF2 PF2
input output input output
1, 2, 4
—
Areas 2 to 5
are all normal space
0 1
PF1 input PF1
output
0
— Any
DRAM*
space
area is
16-bit bus
space
—
1 0 1
LCAS*
PF2 PF2 PF2
input output output
0
—
0 1
PF1 input PF1
output
Rev. 2.00, 05/03, page 367 of 820
3, 7
1
All DRAM* space areas are 8-bit
bus space, or areas 2 to 5 are all
normal space
— 1
— 0 1
CS6
PF2
input output
7
1
Any of Areas 2 to 5
areas are all normal space
2 to 5 is
DRAM*
space
— 0
UCAS*
PF1 input
output
0
0 1
PF2 PF2
input output
1
PF1
output