Figure 7.18 Example Of Short Address Mode Transfer - Renesas H8S/2368 Series Hardware Manual

Address bus
Bus release

Figure 7.18 Example of Short Address Mode Transfer

A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle.
Full Address Mode (Cycle Steal Mode): Figure 7.19 shows a transfer example in which TEND
output is enabled and word-size full address mode transfer (cycle steal mode) is performed from
external 16-bit, 2-state access space to external 16-bit, 2-state access space.
Rev. 2.00, 05/03, page 250 of 820
DMA DMA
read
write
Bus release
DMA DMA
read
write
Bus release
DMA DMA DMA
read
write dead
Last transfer
cycle
Bus
release