Usage Notes; 10.10.1 Module Stop Mode Setting; 10.10.2 Input Clock Restrictions; Figure 10.43 Timing For Status Flag Clearing By Dtc/Dmac Activation - Renesas H8S/2368 Series Hardware Manual

φ
Address
Status flag
Interrupt
request
signal
Note: * Not supported by the H8S/2366.
Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC* Activation
10.10

Usage Notes

10.10.1 Module Stop Mode Setting

TPU operation can be disabled or enabled using the module stop control register. The initial
setting is for TPU operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 22, Power-Down Modes.

10.10.2 Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.44 shows the input clock
conditions in phase counting mode.
Rev. 2.00, 05/03, page 444 of 820
DTC/DMAC* DTC/DMAC*
read cycle write cycle
T T T
1 2 1
Destination
Source address
address
T
2