Renesas H8S/2368 Series Hardware Manual page 23

5.4.1 External Interrupts ............................................................................................... 90
5.4.2 Internal Interrupts................................................................................................. 91
5.5 Interrupt Exception Handling Vector Table...................................................................... 92
5.6 Interrupt Control Modes and Interrupt Operation ............................................................. 97
5.6.1 Interrupt Control Mode 0 ..................................................................................... 97
5.6.2 Interrupt Control Mode 2 ..................................................................................... 99
5.6.3 Interrupt Exception Handling Sequence .............................................................. 100
5.6.4 Interrupt Response Times .................................................................................... 102
5.6.5 DTC and DMAC* Activation by Interrupt .......................................................... 103
5.7 Usage Notes ...................................................................................................................... 103
5.7.1 Contention between Interrupt Generation and Disabling..................................... 103
5.7.2 Instructions that Disable Interrupts ...................................................................... 104
5.7.3 Times when Interrupts are Disabled .................................................................... 104
5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 104
5.7.5 Change of IRQ Pin Select Register (ITSR) Setting ............................................. 105
5.7.6 Note on IRQ Status Register (ISR) ...................................................................... 105
Section 6 Bus Controller (BSC)........................................................................ 107
6.1 Features ............................................................................................................................. 107
6.2 Input/Output Pins .............................................................................................................. 109
6.3 Register Descriptions ........................................................................................................ 110
6.3.1 Bus Width Control Register (ABWCR)............................................................... 111
6.3.2 Access State Control Register (ASTCR) ............................................................. 111
6.3.3 Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)........................................... 112
6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................ 117
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)................... 118
6.3.5
6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL).............................. 120
6.3.7 Bus Control Register (BCR) ................................................................................ 121
6.3.8 DRAM Control Register (DRAMCR) ................................................................. 123
6.3.9 DRAM Access Control Register (DRACCR) ...................................................... 128
6.3.10 Refresh Control Register (REFCR) ..................................................................... 129
6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 132
6.3.12 Refresh Time Constant Register (RTCOR) ......................................................... 132
6.4 Operation .......................................................................................................................... 132
6.4.1 Area Division ....................................................................................................... 132
6.4.2 Bus Specifications................................................................................................ 134
6.4.3 Memory Interfaces ............................................................................................... 136
6.4.4 Chip Select Signals .............................................................................................. 137
6.5 Basic Bus Interface ........................................................................................................... 138
6.5.1 Data Size and Data Alignment............................................................................. 138
6.5.2 Valid Strobes........................................................................................................ 139
Rev. 2.00, 05/03, page xxiii of lii