Figure 24.14 Dram Access Timing: Two-State Access, One Wait - Renesas H8S/2368 Series Hardware Manual

A23 to A0
,
,
,
Read
D15 to D0
,
,
Write
D15 to D0
,
Notes:
timing: when DDS = 0
timing: when RAST = 0
Tcw : Wait cycle inserted by programmable wait function
Tcwp: Wait cycle inserted by pin wait function

Figure 24.14 DRAM Access Timing: Two-State Access, One Wait

T T
p r
T T T
c1 cw
t t t
WTS WTH WTS
Rev. 2.00, 05/03, page 753 of 820
T
cwp c2
t
WTH