Figure 6.45 Example Of Idle Cycle Operation (Write After Read) - Renesas H8S/2368 Series Hardware Manual

Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.45 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Address bus
(area A)
(area B)
Data bus
(a) No idle cycle insertion

Figure 6.45 Example of Idle Cycle Operation (Write after Read)

Read after Write: If an external read occurs after an external write while the ICIS2 bit is set to 1
in BCR, an idle cycle is inserted at the start of the read cycle.
Figure 6.46 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not
inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an
external device. In (b), an idle cycle is inserted, and a data collision is prevented.
Rev. 2.00, 05/03, page 180 of 820
Bus cycle A Bus cycle B
T T T T T
1 2 3 1 2
y
Long output floating time
(ICIS0 = 0)
Bus cycle A
T
1
Address bus
(area A)
(area B)
Data bus
Data collision
(b) Idle cycle insertion
(ICIS0 = 1, initial value)
Bus cycle B
T T T T T
2 3 i 1 2
Idle cycle