Figure 7.19 Example Of Full Address Mode Transfer (Cycle Steal) - Renesas H8S/2368 Series Hardware Manual

Address bus
Bus release

Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)

A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one bus cycle is executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Full Address Mode (Burst Mode): Figure 7.20 shows a transfer example in which TEND output
is enabled and word-size full address mode transfer (burst mode) is performed from external 16-
bit, 2-state access space to external 16-bit, 2-state access space.
DMA DMA
read write
Bus release
DMA DMA
read write
Bus release
Rev. 2.00, 05/03, page 251 of 820
DMA DMA DMA
read write dead
Last transfer
cycle
Bus
release