Renesas H8S/2368 Series Hardware Manual page 37

Section 1 Overview
Figure 1.1 Internal Block Diagram of H8S/2367, H8S/2365, and H8S/2363 .............................3
Figure 1.2 Internal Block Diagram of H8S/2366 ........................................................................4
Figure 1.3 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363........................................5
Figure 1.4 Pin Arrangement of H8S/2366...................................................................................6
Figure 1.5 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363........................................7
Figure 1.6 Pin Arrangement of H8S/2366...................................................................................8
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode) .................................................................25
Figure 2.2 Stack Structure in Normal Mode .............................................................................25
Figure 2.3 Exception Vector Table (Advanced Mode) .............................................................26
Figure 2.4 Stack Structure in Advanced Mode .........................................................................27
Figure 2.5 Memory Map ...........................................................................................................28
Figure 2.6 CPU Internal Registers ............................................................................................29
Figure 2.7 Usage of General Registers......................................................................................30
Figure 2.8 Stack ........................................................................................................................31
Figure 2.9 General Register Data Formats (1) ..........................................................................34
Figure 2.9 General Register Data Formats (2) ..........................................................................35
Figure 2.10 Memory Data Formats .............................................................................................36
Figure 2.11 Instruction Formats (Examples)...............................................................................48
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ....................51
Figure 2.13 State Transitions.......................................................................................................55
Section 3 MCU Operating Modes
Figure 3.1 H8S/2367 Memory Map (1).....................................................................................62
Figure 3.2 H8S/2367 Memory Map (2).....................................................................................63
Figure 3.3 H8S/2366 Memory Map (1).....................................................................................64
Figure 3.4 H8S/2366 Memory Map (2).....................................................................................65
Figure 3.5 H8S/2365 Memory Map (1).....................................................................................66
Figure 3.6 H8S/2365 Memory Map (2).....................................................................................67
Figure 3.7 H8S/2363 Memory Map ..........................................................................................68
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled) ...........................72
Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled) ..........................73
Figure 4.3 Stack Status after Exception Handling.....................................................................76
Figure 4.4 Operation when SP Value Is Odd ............................................................................77
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller ....................................................................80
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ..........................................................91
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0 .....................................................................................98
Figures
Rev. 2.00, 05/03, page xxxvii of lii