Renesas H8S/2368 Series Hardware Manual page 67

Type Symbol
Address bus A23 to
A0
Data bus D15 to
D0
CS7 to
Bus control
CS0
AS
RD
HWR
LWR
BREQ
BREQO
BACK
UCAS*
Pin No.
TFP-120 QFP-128
29 to 23, 33 to 27,
21 to 18, 25 to 22,
16 to 9, 20 to 13,
7 to 3 11 to 7
68 to 61, 76 to 69,
59, 65,
57 to 51 63 to 57
29,71,70, 33,79,78,
106, 116,102,
92 to 89 101,98,97
75 83
74 82
73 81
72 80
108 118
106 116
107 117
70 78
I/O Function
Output Address output pins.
Input/ These pins constitute a bidirectional
output data bus.
Output Signals that select division areas 7 to
0 in the external address space.
Output When this pin is low, it indicates that
address output on the address bus is
valid.
Output When this pin is low, it indicates that
the external address space is being
read.
Output Strobe signal indicating that external
address space is to be written, and
the upper half (D15 to D8) of the data
bus is enabled.
Write enable signal for accessing the
DRAM space.
Output Strobe signal indicating that external
address space is to be written, and
the lower half (D7 to D0) of the data
bus is enabled.
Input The external bus master requests the
bus to this LSI.
Input External bus request signal when the
internal bus master accesses the
external space in external bus
release state.
Output Indicates the bus is released to the
external bus master.
Output Upper column address strobe signal
for accessing the 16-bit DRAM
space.
Column address strobe signal for
accessing the 8-bit DRAM space.
Rev. 2.00, 05/03, page 15 of 820