Figure 7.31 Example Of Dreq Pin Low Level Activated Single Address Mode Transfer - Renesas H8S/2368 Series Hardware Manual

Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low
level.
Address bus
DMA control Idle
Channel
[1] Acceptance after transfer enabling; the
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
(As in [1], the
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.31 Example of DREQ
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Rev. 2.00, 05/03, page 262 of 820
Bus release DMA single
Transfer source/
Single
Request clear
Request
Minimum of
2 cycles
[1] [2] [3]
pin low level is sampled on the rising edge of , and the request is held.)
DREQ Pin Low Level Activated Single Address Mode Transfer
DREQ DREQ
Bus release
destination
Idle
period Request
Minimum of
2 cycles
[4] [5]
Acceptance resumes
pin low level is sampled on the rising edge of ,
Bus
DMA single
release
Transfer source/
destination
Single Idle
Request clear
period
[6] [7]
Acceptance resumes