Table of Contents
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2.8
Processing States............................................................................................................... 54
2.9
Usage Note........................................................................................................................ 55
2.9.1
Note on Bit Manipulation Instructions................................................................. 55
Section 3 MCU Operating Modes ..................................................................... 57
3.1
Operating Mode Selection ................................................................................................ 57
3.2
Register Descriptions ........................................................................................................ 58
3.2.1
Mode Control Register (MDCR) ......................................................................... 58
3.2.2
System Control Register (SYSCR) ...................................................................... 58
3.3
Operating Mode Descriptions ........................................................................................... 60
3.3.1
Mode 1 ................................................................................................................. 60
3.3.2
Mode 2 ................................................................................................................. 60
3.3.3
Mode 3 ................................................................................................................. 60
3.3.4
Mode 4 ................................................................................................................. 60
3.3.5
Mode 7 ................................................................................................................. 61
3.3.6
Pin Functions ....................................................................................................... 61
3.4
Memory Map in Each Operating Mode ............................................................................ 62
Section 4 Exception Handling ........................................................................... 69
4.1
Exception Handling Types and Priority............................................................................ 69
4.2
Exception Sources and Exception Vector Table ............................................................... 69
4.3
Reset ................................................................................................................................. 71
4.3.1
Reset Exception Handling ................................................................................... 71
4.3.2
Interrupts after Reset............................................................................................ 73
4.3.3
On-Chip Peripheral Functions after Reset Release .............................................. 73
4.4
Traces................................................................................................................................ 74
4.5
Interrupts........................................................................................................................... 74
4.6
Trap Instruction................................................................................................................. 75
4.7
Stack Status after Exception Handling.............................................................................. 76
4.8
Usage Notes ...................................................................................................................... 77
Section 5 Interrupt Controller............................................................................ 79
5.1
Features............................................................................................................................. 79
5.2
Input/Output Pins .............................................................................................................. 81
5.3
Register Descriptions ........................................................................................................ 81
5.3.1
Interrupt Control Register (INTCR) .................................................................... 82
5.3.2
Interrupt Priority Registers A to K (IPRA to IPRK)............................................ 82
5.3.3
IRQ Enable Register (IER) .................................................................................. 84
5.3.4
IRQ Sense Control Register L (ISCRL)............................................................... 85
5.3.5
IRQ Status Register (ISR).................................................................................... 88
5.3.6
IRQ Pin Select Register (ITSR) ........................................................................... 89
5.3.7
Software Standby Release IRQ Enable Register (SSIER) ................................... 90
5.4
Interrupt Sources............................................................................................................... 90
Rev. 2.00, 05/03, page xxii of lii
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