Renesas H8S/2368 Series Hardware Manual page 15

Item
21.2.2 External Clock Input
21.4 Frequency Divider
21.5.3 Notes on Board
Design
Figure 21.7 Recommended
External Circuitry for PLL
Circuit
Section 22 Power-Down
Modes
Table 22.1 Operating
Modes and Internal States of
the LSI
22.2.1 Clock Division Mode
22.4.6 Notes on Clock
Division Mode
23.1 Register Addresses
(Address Order)
Page Revision (See Manual for Details)
679 Description added in the 5th line.
Table 21.3 shows the input conditions for the external
clock.
The frequency of an external clock to be input should
be 8 MHz to 25 MHz.
681 Description amended in the 11th line.
The frequency divider divides the PLL output clock to
generate a 1/2 or 1/4 clock.
682 Description of (Values are preliminary recommended
values.) deleted.
684 Table amended.
Operating State
External NMI
interrupts
IRQ0 to 7
A/D
Peripheral
functions
SCI
IIC2
Notes added.
Notes: *3 TDR, SSR, and RDR are halted (reset)
*4 BC2 to BC0 are halted (reset) and other
690 Description amended in the 5th line.
In clock division mode, the CPU, bus masters, and
on-chip peripheral functions all operate on the
operating clock (1/2 or 1/4) specified by bits SCK2 to
SCK0.
697 Newly added.
701 IRQ sense control register H deleted.
Register Name
IRQ pin select register
Software standby release IRQ enable
register
IRQ sense control register L
High Clock
Speed Division Sleep Module
Mode Mode Mode Stop Mode
Functions Functions Functions Functions
Functions Functions Functions Halted
(Retained)
Functions Functions Functions Halted*
(Reset/
Retained)
Functions Functions Functions Halted*
(Reset/
Retained)
and other registers are halted (retained).
registers are halted (retained).
Abbrevia-
tion Bit No. Address
ITSR 16 H'FE16
SSIER 16 H'FE18
ISCRL 16 H'FE1C
Rev. 2.00, 05/03, page xv of lii
All Module Software Hardware
Clock Stop Standby Standby
Mode Mode Mode
Functions Functions Halted
Halted Halted Halted
(Retained) (Retained) (Reset)
3 3 3
Halted* Halted* Halted
(Reset/ (Reset/ (Reset)
Retained) Retained)
4 4 4
Halted* Halted* Halted
(Reset/ (Reset/ (Reset)
Retained) Retained)
Data Access
Module Width States
INT 16 2
INT 16 2
INT 16 2