Renesas H8S/2368 Series Hardware Manual page 183

Bit Bit Name
3 SLFRF
2 TPCS2
1 TPCS1
0 TPCS0
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Self-Refresh Enable
If this bit is set to 1, DRAM self-refresh mode is
selected when a transition is made to the
software standby state. This bit is valid when
the RFSHE bit is set to 1, enabling refresh
operations. It is cleared after recovery from
software standby mode.
0: Self-refreshing is disabled
1: Self-refreshing is enabled
Self-Refresh Precharge Cycle Control
These bits select the number of states in the
precharge cycle immediately after self-
refreshing.
The number of states in the precharge cycle
immediately after self-refreshing are added to
the number of states set by bits TPC1 and
TPC0 in DRACCR.
000: [TPC set value] states
001: [TPC set value + 1] states
010: [TPC set value + 2] states
011: [TPC set value + 3] states
100: [TPC set value + 4] states
101: [TPC set value + 5] states
110: [TPC set value + 6] states
111: [TPC set value + 7] states
Rev. 2.00, 05/03, page 131 of 820