Renesas H8S/2368 Series Hardware Manual page 261

Bit Bit Name

10
to
8
Legend
x: Don't care
• DMACR_0B and DMACR_1B
Bit Bit Name

7
6 DAID
5 DAIDE
4 —
3 DTF3
2 DTF2
1 DTF1
0 DTF0
Initial Value R/W
0 R/W
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Reserved
Though these bits can be read from or written
to, the write value should always be 0.
Description
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Destination Address Increment/Decrement
Destination Address Increment/Decrement
Enable
These bits specify whether destination address
register MARB is to be incremented,
decremented, or left unchanged, when data
transfer is performed.
00: MARB is fixed
01: MARB is incremented after a data transfer
•
When DTSZ = 0, MARB is incremented by 1
•
When DTSZ = 1, MARB is incremented by 2
10: MARB is fixed
11: MARB is decremented after a data transfer
•
When DTSZ = 0, MARB is decremented by
1
•
When DTSZ = 1, MARB is decremented by
2
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Data Transfer Factor 3 to 0
These bits select the data transfer factor
(activation source). The factors that can be
specified differ between normal mode and block
transfer mode.
Rev. 2.00, 05/03, page 209 of 820