Next Data Enable Registers H, L (Nderh, Nderl) - Renesas H8S/2368 Series Hardware Manual

11.3.1

Next Data Enable Registers H, L (NDERH, NDERL)

NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the
PPG, set the corresponding DDR to 1.
• NDREH
Bit Bit Name
7 NDER15
6 NDER14
5 NDER13
4 NDER12
3 NDER11
2 NDER10
1 NDER9
0 NDER8
• NDERL
Bit Bit Name
7 NDER7
6 NDER6
5 NDER5
4 NDER4
3 NDER3
2 NDER2
1 NDER1
0 NDER0
Rev. 2.00, 05/03, page 456 of 820
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Next Data Enable 15 to 8
When a bit is set to 1, the value in the
corresponding NDRH bit is transferred to the
PODRH bit by the selected output trigger. Values
are not transferred from NDRH to PODRH for
cleared bits.
Description
Next Data Enable 7 to 0
When a bit is set to 1, the value in the
corresponding NDRL bit is transferred to the
PODRL bit by the selected output trigger. Values
are not transferred from NDRL to PODRL for
cleared bits.