Renesas H8S/2368 Series Hardware Manual page 29

10.4 Operation .......................................................................................................................... 411
10.4.1 Basic Functions.................................................................................................... 411
10.4.2 Synchronous Operation........................................................................................ 416
10.4.3 Buffer Operation .................................................................................................. 418
10.4.4 Cascaded Operation ............................................................................................. 422
10.4.5 PWM Modes ........................................................................................................ 424
10.4.6 Phase Counting Mode .......................................................................................... 429
10.5 Interrupts ........................................................................................................................... 435
10.6 DTC Activation................................................................................................................. 437
10.7 DMAC Activation............................................................................................................. 437
10.8 A/D Converter Activation ................................................................................................. 437
10.9 Operation Timing.............................................................................................................. 438
10.9.1 Input/Output Timing ............................................................................................ 438
10.9.2 Interrupt Signal Timing........................................................................................ 441
10.10 Usage Notes ...................................................................................................................... 444
10.10.1 Module Stop Mode Setting .................................................................................. 444
10.10.2 Input Clock Restrictions ...................................................................................... 444
10.10.3 Caution on Cycle Setting ..................................................................................... 445
10.10.4 Contention between TCNT Write and Clear Operations ..................................... 445
10.10.5 Contention between TCNT Write and Increment Operations.............................. 446
10.10.6 Contention between TGR Write and Compare Match ......................................... 447
10.10.7 Contention between Buffer Register Write and Compare Match ........................ 447
10.10.8 Contention between TGR Read and Input Capture.............................................. 448
10.10.9 Contention between TGR Write and Input Capture............................................. 449
10.10.10 Contention between Buffer Register Write and Input Capture ........................ 449
10.10.11 Contention between Overflow/Underflow and Counter Clearing.................... 450
10.10.12 Contention between TCNT Write and Overflow/Underflow........................... 451
10.10.13 Multiplexing of I/O Pins .................................................................................. 451
10.10.14 Interrupts and Module Stop Mode ................................................................... 451
Section 11 Programmable Pulse Generator (PPG) ........................................... 453
11.1 Features ............................................................................................................................. 453
11.2 Input/Output Pins .............................................................................................................. 455
11.3 Register Descriptions ........................................................................................................ 455
11.3.1 Next Data Enable Registers H, L (NDERH, NDERL)......................................... 456
11.3.2 Output Data Registers H, L (PODRH, PODRL).................................................. 457
11.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 458
11.3.4 PPG Output Control Register (PCR).................................................................... 460
11.3.5 PPG Output Mode Register (PMR)...................................................................... 461
11.4 Operation .......................................................................................................................... 463
11.4.1 Output Timing...................................................................................................... 464
11.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 465
11.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 466
Rev. 2.00, 05/03, page xxix of lii