Register
Name
Reset
ETCR_0A
Initialized
MAR_0BH
Initialized
MAR_0BL
Initialized
IOAR_0B
Initialized
ETCR_0B
Initialized
MAR_1AH
Initialized
MAR_1AL
Initialized
IOAR_1A
Initialized
ETCR_1A
Initialized
MAR_1BH
Initialized
MAR_1BL
Initialized
IOAR_1B
Initialized
ETCR_1B
Initialized
DMAWER
Initialized
DMATCR
Initialized
DMACR_0A
Initialized
DMACR_0B
Initialized
DMACR_1A
Initialized
DMACR_1B
Initialized
DMABCRH
Initialized
DMABCRL
Initialized
DTCERA
Initialized
DTCERB
Initialized
DTCERC
Initialized
DTCERD
Initialized
DTCERE
Initialized
DTCERF
Initialized
DTCERG
Initialized
DTVECH
Initialized
DTVECR
Initialized
INTCR
Initialized
IER
Initialized
ISR
Initialized
High-
Clock
Speed
Division Sleep
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Module
All Module
Software
Stop
Clock Stop
Standby
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Rev. 2.00, 05/03, page 727 of 820
Hardware
Standby
Module
Initialized
DMAC*
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
DTC
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
INT
Initialized
Initialized