Renesas H8S/2368 Series Hardware Manual page 362

• P12/PO10*
1
/TIOCC0/TCLKA/TEND0*
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2
to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10*
1
bit TEE0* in DMATCR of DMAC and bit P12DDR.
1
TEE0*
TPU channel 2 (1) in table below
settings
P12DDR
1
NDER10*
Pin function TIOCO0 output
Notes: *1 Not supported by the H8S/2366.
*2 TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
*3 TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100.
TCLKA input when phase counting mode is set for channels 1 and 5.
TPU channel 0
settings
MD3 to MD0
IOC3 to IOC0 B'0000
B'0100
B'1xxx
CCLR2, CCLR0
Output function
x: Don't care
Note: *4 TIOCD0 output disabled.
Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0.
Rev. 2.00, 05/03, page 310 of 820
—
—
P12 input
(2) (1)
B'0000
B'0001 to
B'0011
B'0101 to
B'0111
— —
— Output
compare
output
1
0
(2) in table below
0 1
— 0
P12 output
TIOCC0 input*
TCLKA input*
(2) (1)
B'001x B'0010
B'xx00 Other
than B'xx00
— —
— PWM*
mode 1
output
1
in NDERH,
1
1
1
PO10 output*
2
3
(1)
B'0011
Other than B'xx00
Other than
B'101
4
PWM mode
2 output
1
—
—
—
TEND0
1
output*
(2)
B'101
—