Figure 16.1 Block Diagram Of A/D Converter - Renesas H8S/2368 Series Hardware Manual

AVCC
Vref
10-bit A/D
AVSS
AN0
AN1
AN2
AN3
Sample-and-
AN4
hold circuit
AN5
AN6
AN7
AN12
AN13
Legend
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
Rev. 2.00, 05/03, page 620 of 820
Module data bus
A A A
D D D
D D D
R R R
A B C
+
–
Comparator
ADDRD: A/D data register D
ADDRE: A/D data register E
ADDRF: A/D data register F
ADDRG: A/D data register G
ADDRH: A/D data register H

Figure 16.1 Block Diagram of A/D Converter

A A A A A
D D D D D
D D D D D
R R R R R
D E F G H
Control circuit
Internal data bus
A A
D D
C C
S R
R
ADI interrupt
signal
Conversion start
trigger from 8-bit
timer or TPU