Renesas H8S/2368 Series Hardware Manual page 177

Bit Bit Name
6 RCDM
5 DDS
−
4 and
3
Initial Value R/W
0 R/W
0 R/W
0 R/W
Description
RAS Down Mode
When access to DRAM space is interrupted by
an access to normal space, an access to an
internal I/O register, etc., this bit selects whether
the RAS signal is held low while waiting for the
next DRAM access (RAS down mode), or is
driven high again (RAS up mode). The setting
of this bit is valid only when the BE bit is set to
1.
If this bit is cleared to 0 when set to 1 in the
RAS down state, the RAS down state is cleared
at that point, and RAS goes high.
0: RAS up mode selected for DRAM space
access
1: RAS down mode selected for DRAM space
access
DMAC Single Address Transfer Option
Selects whether full access is always performed
or burst access is enabled when DMAC single
address transfer is performed on the DRAM
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM burst access, DMAC single
address transfer is performed in full access
mode regardless of the setting of this bit.
This bit has no effect on other bus master
external accesses or DMAC dual address
transfers.
0: Full access is always executed
1: Burst access is enabled
Reserved
Though these bits can be read from or written
to, the write value should always be 0.
Rev. 2.00, 05/03, page 125 of 820