Renesas H8S/2368 Series Hardware Manual page 30

11.4.4 Non-Overlapping Pulse Output............................................................................ 467
11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output.............................. 468
11.4.6 Example of Non-Overlapping Pulse Output
(Example of Four-Phase Complementary Non-Overlapping Output) ................. 469
11.4.7 Inverted Pulse Output .......................................................................................... 471
11.4.8 Pulse Output Triggered by Input Capture ............................................................ 472
11.5 Usage Notes ...................................................................................................................... 472
11.5.1 Module Stop Mode Setting .................................................................................. 472
11.5.2 Operation of Pulse Output Pins............................................................................ 472
Section 12 8-Bit Timers (TMR) ........................................................................473
12.1 Features............................................................................................................................. 473
12.2 Input/Output Pins .............................................................................................................. 475
12.3 Register Descriptions ........................................................................................................ 475
12.3.1 Timer Counter (TCNT)........................................................................................ 475
12.3.2 Time Constant Register A (TCORA)................................................................... 476
12.3.3 Time Constant Register B (TCORB) ................................................................... 476
12.3.4 Timer Control Register (TCR)............................................................................. 476
12.3.5 Timer Control/Status Register (TCSR)................................................................ 478
12.4 Operation .......................................................................................................................... 481
12.4.1 Pulse Output......................................................................................................... 481
12.5 Operation Timing.............................................................................................................. 482
12.5.1 TCNT Incrementation Timing ............................................................................. 482
12.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs ................. 483
12.5.3 Timing of Timer Output when Compare-Match Occurs...................................... 483
12.5.4 Timing of Compare Match Clear ......................................................................... 484
12.5.5 Timing of TCNT External Reset.......................................................................... 484
12.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 485
12.6 Operation with Cascaded Connection............................................................................... 485
12.6.1 16-Bit Counter Mode ........................................................................................... 485
12.6.2 Compare Match Count Mode............................................................................... 486
12.7 Interrupts........................................................................................................................... 486
12.7.1 Interrupt Sources and DTC Activation ................................................................ 486
12.7.2 A/D Converter Activation.................................................................................... 487
12.8 Usage Notes ...................................................................................................................... 488
12.8.1 Contention between TCNT Write and Clear........................................................ 488
12.8.2 Contention between TCNT Write and Increment ................................................ 488
12.8.3 Contention between TCOR Write and Compare Match ...................................... 489
12.8.4 Contention between Compare Matches A and B ................................................. 490
12.8.5 Switching of Internal Clocks and TCNT Operation ............................................ 491
12.8.6 Mode Setting with Cascaded Connection ............................................................ 493
12.8.7 Interrupts in Module Stop Mode.......................................................................... 493
Rev. 2.00, 05/03, page xxx of lii