Register Descriptions - Renesas H8S/2368 Series Hardware Manual

Name
Output enable*
Wait
Bus request
Bus request acknowledge
Bus request output
Data transfer acknowledge
1 (DMAC) *
Data transfer acknowledge
0 (DMAC) *
Note: * Not supported by the H8S/2366.
6.3

Register Descriptions

The bus controller has the following registers.
• Bus width control register (ABWCR)
• Access state control register (ASTCR)
• Wait control register AH (WTCRAH)
• Wait control register AL (WTCRAL)
• Wait control register BH (WTCRBH)
• Wait control register BL (WTCRBL)
• Read strobe timing control register (RDNCR)
• CS assertion period control register H (CSACRH)
• CS assertion period control register L (CSACRL)
• Area 0 burst ROM interface control register (BROMCRH)
• Area 1 burst ROM interface control register (BROMCRL)
• Bus control register (BCR)
• DRAM control register (DRAMCR)*
• DRAM access control register (DRACCR)*
• Refresh control register (REFCR)*
• Refresh timer counter (RTCNT)*
• Refresh time constant register (RTCOR)*
Note: * Not supported by the H8S/2366.
Rev. 2.00, 05/03, page 110 of 820
Symbol I/O
OE*
Output
WAIT
Input
BREQ
Input
BACK
Output
BREQO
Output
DACK1*
Output
DACK0*
Output
Function
Output enable signal for the DRAM space.
Wait request signal when accessing
external address space.
Request signal for release of bus to
external bus master.
Acknowledge signal indicating that bus has
been released to external bus master.
External bus request signal used when
internal bus master accesses external
address space when external bus is
released.
Data transfer acknowledge signal for single
address transfer by DMAC channel 1.
Data transfer acknowledge signal for single
address transfer by DMAC channel 0.