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Setting Oscillation Stabilization Time after Clearing Software Standby Mode: Bits STS3 to
STS0 in SBYCR should be set as described below.
Using a Crystal Oscillator:
Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time.
Table 22.2 shows the standby times for operating frequencies and settings of bits STS3 to STS0.
Using an External Clock:
A PLL circuit stabilization time is necessary. Refer to table 22.2 to set the wait time.
Table 22.2 Oscillation Stabilization Time Settings
STS3 STS2 STS1 STS0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
:
Recommended time setting
Note: * φ is the frequency divider output.
Software Standby Mode Application Example: Figure 22.2 shows an example in which a
transition is made to software standby mode at the falling edge on the NMI pin, and software
standby mode is cleared at the rising edge on the NMI pin.
Rev. 2.00, 05/03, page 692 of 820
Standby
Time
33
25
Reserved
—
—
Reserved
—
—
Reserved
—
—
Reserved
—
—
Reserved
—
—
64
1.9
2.6
512
15.5
20.5
1024
31.0
41.0
2048
62.1
81.9
4096
0.12
0.16
16384
0.50
0.66
32765
0.99
1.31
65536
1.99
2.62
131072
3.97
5.24
262144
7.94
10.49
524288
15.89
20.97
φ φ φ φ
* [MHz]
20
13
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.2
4.9
6.4
25.6
39.4
51.2
51.2
78.8
102.4
102.4
157.5
204.8
0.20
0.32
0.41
0.82
1.26
1.64
1.64
2.52
3.28
3.28
5.04
6.55
6.55
10.08
13.11
13.11
20.16
26.21
26.21
40.33
52.43
8
Unit
—
µs
—
—
—
—
8.0
64.0
128.0
256.0
0.51
ms
2.05
4.10
8.19
16.38
32.77
65.54
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