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8.2.1
DTC Mode Register A (MRA) ............................................................................ 277
8.2.2
DTC Mode Register B (MRB)............................................................................. 278
8.2.3
DTC Source Address Register (SAR).................................................................. 278
8.2.4
DTC Destination Address Register (DAR).......................................................... 278
8.2.5
DTC Transfer Count Register A (CRA) .............................................................. 278
8.2.6
DTC Transfer Count Register B (CRB)............................................................... 279
8.2.7
DTC Enable Registers A to G (DTCERA to DTCERG) ..................................... 279
8.2.8
DTC Vector Register (DTVECR)........................................................................ 279
8.3
Activation Sources ............................................................................................................ 280
8.4
Location of Register Information and DTC Vector Table ................................................ 281
8.5
Operation .......................................................................................................................... 284
8.5.1
Normal Mode....................................................................................................... 286
8.5.2
Repeat Mode........................................................................................................ 287
8.5.3
Block Transfer Mode ........................................................................................... 288
8.5.4
Chain Transfer ..................................................................................................... 289
8.5.5
Interrupts.............................................................................................................. 290
8.5.6
Operation Timing................................................................................................. 291
8.5.7
Number of DTC Execution States ....................................................................... 292
8.6
Procedures for Using DTC................................................................................................ 293
8.6.1
Activation by Interrupt......................................................................................... 293
8.6.2
Activation by Software ........................................................................................ 293
8.7
Examples of Use of the DTC ............................................................................................ 293
8.7.1
Normal Mode....................................................................................................... 293
8.7.2
Chain Transfer ..................................................................................................... 294
8.7.3
Chain Transfer when Counter = 0........................................................................ 295
8.7.4
Software Activation ............................................................................................. 296
8.8
Usage Notes ...................................................................................................................... 297
8.8.1
Module Stop Mode Setting .................................................................................. 297
8.8.2
On-Chip RAM ..................................................................................................... 297
8.8.3
DTCE Bit Setting................................................................................................. 297
8.8.4
DMAC Transfer End Interrupt............................................................................. 297
8.8.5
Chain Transfer ..................................................................................................... 297
Section 9 I/O Ports.............................................................................................299
9.1
Port 1................................................................................................................................. 303
9.1.1
Port 1 Data Direction Register (P1DDR)............................................................. 303
9.1.2
Port 1 Data Register (P1DR)................................................................................ 304
9.1.3
Port 1 Register (PORT1)...................................................................................... 304
9.1.4
Pin Functions ....................................................................................................... 305
9.2
Port 2................................................................................................................................. 313
9.2.1
Port 2 Data Direction Register (P2DDR)............................................................. 313
9.2.2
Port 2 Data Register (P2DR)................................................................................ 313
9.2.3
Port 2 Register (PORT2)...................................................................................... 314
Rev. 2.00, 05/03, page xxvi of lii
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