Operation - Renesas H8S/2368 Series Hardware Manual

Origin of
Activation Activation
Source Source
TMR_0 CMIA0
CMIB0
TMR_1 CMIA1
CMIB1
2
DMAC* DMTEND0A
DMTEND0B
DMTEND1A
DMTEND1B
SCI_0 RXI0
TXI0
SCI_1 RXI1
TXI1
SCI_2 RXI2
TXI2
SCI_3 RXI3
TXI3
SCI_4 RXI4
TXI4
Notes: *1 DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
When clearing the software standby state or all-module-clocks-stop mode with an
interrupt, write 0 to the corresponding DTCE bit.
*2 The DMAC is not supported by the H8S/2366.
8.5

Operation

The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information that is already stored in the on-chip RAM and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to the on-
chip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer
data over any required number of channels. There are three transfer modes: normal mode, repeat
mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number
of transfers with a single activation (chain transfer). A setting can also be made to have chain
transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be
performed by the DTC itself.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Rev. 2.00, 05/03, page 284 of 820
DTC
Vector Number Vector Address
72 H'0490
73 H'0492
76 H'0498
77 H'049A
80 H'04A0
81 H'04A2
82 H'04A4
83 H'04A6
89 H'04B2
90 H'04B4
93 H'04BA
94 H'04BC
97 H'04C2
98 H'04C4
101 H'04CA
102 H'04CC
105 H'04D2
106 H'04D4
1
DTCE* Priority
DTCEE3 High
DTCEE2
DTCEE1
DTCEE0
DTCEF7
DTCEF6
DTCEF5
DTCEF4
DTCEF3
DTCEF2
DTCEF1
DTCEF0
DTCEG7
DTCEG6
DTCEF5
DTCEF4
DTCEG3
DTCEG2 Low