Renesas H8S/2368 Series Hardware Manual page 815

Item
WDT Overflow output delay time
SCI Input clock
cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
A/D Trigger input setup time
converter
IIC2 SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA Input fall time
SCL, SDA Input spike pulse
removal time
SDA input bus free time
Start condition input hold
time
Retransmit start condition
input setup time
Stop condition input setup
time
Data input setup time
Data input hold time
SCL, SDA capacitive load
SCL, SDA fall time
Symbol Min
t
WOVD
Asynchronous t
Scyc
Synchronous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
t
TRGS
t
SCL
t
SCLH
t
SCLL
t
Sf
t
SP
t
BUF
t
STAH
t
STAS
t
STOS
t
SDAS
t
SDAH
Cb
t
Sf
Max
— 40
4 —
6 —
0.4 0.6
— 1.5
— 1.5
— 40
40 —
40 —
30 —
12t +600 —
CYC
3t +300 —
CYC
5t +300 —
CYC
— 300
— 1t
CYC
5t —
CYC
3t —
CYC
3t —
CYC
1t +20 —
CYC
0 —
0 —
— 400
— 300
Rev. 2.00, 05/03, page 763 of 820
Unit Test Conditions
ns Figure 24.35
t Figure 24.36
cyc
t
Scyc
t
cyc
ns Figure 24.37
ns
ns
ns Figure 24.38
ns Figure 24.39
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns