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14.3.9 Bit Rate Register
(BRR)
Table 14.9 Maximum Bit
Rate at Various Frequencies
(Smart Card Interface Mode)
(when S = 372)
14.8 IrDA Operation
Table 14.12 Settings of Bits
IrCKS2 to IrCKS0
16.1 Features
Figure 16.1 Block Diagram
of A/D Converter
16.3.3 A/D Control Register
(ADCR)
17.3.2 D/A Control Register
23 (DACR23)
Table 17.2 Control of D/A
Conversion
Section 18 RAM
Page
Revision (See Manual for Details)
Values when operating frequency φ is 7.1424 MHz
536
deleted.
Values when operating frequency φ is 2 MHz to
579
7.3728 MHz deleted.
Values when operating frequency φ is 30 MHz and
33 MHz deleted.
Operating
2400
Frequency
φ (MHz)
78.13
25
110
30
110
33
110
619
Description amended in the 7th line.
• Conversion time: 8.1 µs per channel (at 33 MHz
operation)
620
Figure amended.
AVCC
Vref
AVSS
625
Description added in the 3rd line.
ADCR enables A/D conversion start by an external
trigger input.
It also sets the A/D converter operating mode and the
A/D conversion time.
640
Table amended.
(Error) DAOE1 → (Correction) DAOE3
(Error) DAOE0 → (Correction) DAOE2
643
Table amended.
Product Type Name
H8S/2368
HD64F2367
Series
HD64F2366
HD6432365
HD641363
Bit Rate (bps) (Above)/Bit Period × 3/16 (ms) (Below)
9600
19200
38400
19.53
9.77
4.88
110
110
110
110
110
110
110
110
110
10-bit A/D
RAM
ROM Type
Capacitance
Flash memory version
24 kbytes
30 kbytes
Masked ROM version
16 kbytes
ROMless version
Rev. 2.00, 05/03, page xiii of lii
57600
11520
0
3.26
1.63
110
110
110
RAM Address
H'FF6000 to H'FFBFFF
H'FF4800 to H'FFBFFF
H'FF8000 to H'FFBFFF
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