Figure D.1 Timing Of Address Bus, Rd, Hwr, And Lwr (8-Bit Bus, 3-State Access, No Wait) - Renesas H8S/2368 Series Hardware Manual

Address bus
,
Fetch of 3rd byte of
instruction being
Figure D.1 Timing of Address Bus, RD
Rev. 2.00, 05/03, page 796 of 820
R: W 2nd
Fetch of 4th byte of
instruction being
executed executed
RD, HWR RD RD
High
Internal
operation
Fetch of 1st byte of
brunch destination
instruction
HWR, and LWR HWR HWR LWR (8-bit bus, 3-state access, no wait) LWR LWR
R: W EA
Fetch of 2nd byte of
brunch destination
instruction