External Trigger Input Timing; Interrupts; Figure 16.3 External Trigger Input Timing; Table 16.5 A/D Converter Interrupt Source - Renesas H8S/2368 Series Hardware Manual

16.4.4

External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3 shows the
timing.
Internal trigger signal
ADST
16.5

Interrupts

The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
Setting the ADIE bit to 1 enables an ADI interrupt requests while the bit ADF in ADCSR is set to
1 after A/D conversion is completed. The DTC or DMAC* can be activated by an ADI interrupt.
Having the converted data read by the DTC or DMAC* in response to an ADI interrupt enables
continuous conversion to be achieved without imposing a load on software.
Note: * Not supported by the H8S/2366.

Table 16.5 A/D Converter Interrupt Source

Name Interrupt Source
ADI End of conversion
Note: * Not supported by the H8S/2366.

Figure 16.3 External Trigger Input Timing

Interrupt Flag
ADF
A/D conversion
DTC Activation DMAC* Activation
Possible Possible
Rev. 2.00, 05/03, page 629 of 820