Renesas H8S/2368 Series Hardware Manual page 9

Main Revisions and Additions in this Edition
Item
All
1.1 Features
1.2 Block Diagram
Figure 1.1 Internal Block
Diagram of H8S/2367,
H8S/2365, and H8S/2363
Figure 1.2 Internal Block
Diagram of H8S/2366
1.3.1 Pin Arrangement
Figure 1.3 Pin Arrangement
of H8S/2367, H8S/2365, and
H8S/2363
Figure 1.4 Pin Arrangement
of H8S/2366
Page Revision (See Manual for Details)
H8S/2366 added.
1 Table amended.
ROM Type
Flash memory version
Masked ROM version
ROMless version
3 Description added in the 2nd line.
Figures 1.1 and 1.2 show the internal block diagrams
of this LSI.
Figure and its title amended.
C bus interface (option) →
2
(Error) I
(Correction) I
4 Newly added.
5 Description added in the 3rd line.
Figures 1.3 to 1.6 show the pin arrangements of this
LSI.
Pin names of pins 70 and 71 amended and note
added to pin 30.
Note: * This is an emulator enable pin. Normally, this
pin should be set to low. If this pin goes high in
the flash memory version, the on-chip
emulator function is enabled. At this time, pins
P53, PG4, PG5, PG6, and WDTOVF function
only for the on-chip emulator.
6 Newly added.
Model ROM RAM
HD64F2367 384 kbytes 24 kbytes
HD64F2366 384 kbytes 30 kbytes
HD6432365 256 kbytes 16 kbytes
HD6412363 16 kbytes
2
C bus interface 2 (option)
Rev. 2.00, 05/03, page ix of lii
Remarks
In planning stage