Renesas H8S/2368 Series Hardware Manual page 10

Item
1.3.1 Pin Arrangement
Figure 1.5 Pin Arrangement
of H8S/2367, H8S/2365, and
H8S/2363
Figure 1.6 Pin Arrangement
of H8S/2366
3.3.6 Pin Functions
Table 3.2 Pin Functions in
Each Operating Mode
3.4 Memory Map in Each
Operating Mode
Figure 3.3 H8S/2366
Memory Map (1)
Figure 3.4 H8S/2366
Memory Map (2)
Figure 3.7 H8S/2363
Memory Map
5.1 Features
Figure 5.1 Block Diagram
of Interrupt Controller
5.3 Register Descriptions
5.3.4 IRQ Sense Control
Register L (ISCRL)
Rev. 2.00, 05/03, page x of lii
Page Revision (See Manual for Details)
7 Pin name of pin 86 amended and note added to pin
34.
Notes: *1 The NC pin should be fixed to Vss or should
*2This is an emulator enable pin. Normally,
8 Newly added.
61 Note *2 added
Note: *2 Setting not allowed on no-ROM versions.
64, 65 Newly added.
68 Figure amended.
(Error) H'FF6000 → (Correction) H'FF8000
80 Register name amended.
(Error) ISCR → (Correction) ISCRL
81 Register name amended in the 6th line.
•
IRQ sense control register L (ISCRL)
85 Title amended.
Description amended in the 2nd line.
(Error) ISCR → (Correction) ISCRL
be open.
this pin should be set to low. If this pin goes
high in the flash memory version, the on-
chip emulator function is enabled. At this
time, pins P53, PG4, PG5, PG6, and
WDTOVF function only for the on-chip
emulator.